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David Clark Keezer
讲席教授
IEEE Life Fellow
所属单位:
信息科学与技术学部
电子科学与技术学院
行政职务:
联系信息:
dkeezer@eitech.edu.cn
研究方向:

高性能电子系统设计与测试方法(ATE)研究;超高速逻辑系统设计及先进电子封装研究:太赫兹波段超高速逻辑系统研究、器件与系统的封装方法研究;VLSI测试、容错设计:基于新兴存储器件的神经形态计算系统故障分析和容错设计研究。


背景介绍

Dr. David Keezer (Life Fellow, IEEE) received the B.S. degree from the University of California, Berkeley, CA, the M.S. degree from the California Institute of Technology, Pasadena, CA, the Ph.D. degree from Carnegie Mellon University, Pittsburg, PA, and the MBA degree from the Florida Institute of Technology, Melbourne, FL, USA.

He previously served as an Associate Professor at the University of South Florida, Tampa, FL, USA, and held industry positions at Harris Corporation, Melbourne, FL, Intel Corporation, Santa Clara,, CA and IBM Corporation, San Jose, CA USA. In 1995, he joined the Georgia Institute of Technology, Atlanta, GA, USA, where he was a Professor of Electrical and Computer Engineering. He has had close collaboration with Hewlett Packard, IBM in Bromont, Canada and Samsun, Korea. Since 2022, Dr. Keezer has been a Chair Professor of Information Science and Technology at the Eastern Institute of Technology, Ningbo, China.

Until 2026, Dr. Keezer has authored about 300 publications in the field of electronics testing. He was elevated to IEEE Fellow in 2010 and IEEE Life Fellow in 2024. His current research focuses on advancing electronics testing methodologies for high-speed (GHz/THz) digital integrated circuits and systems.


研究领域

1、高性能电子系统设计与测试方法(ATE)研究:使当前自动测试设备(ATE)的测试速率拓展至其原性能水平的10倍以上,并大大降低测试成本,推动了世界高速集成电路测试技术的进步;

2、超高速逻辑系统设计及先进电子封装研究:太赫兹波段超高速逻辑系统研究、器件与系统的封装方法研究;

3VLSI测试、容错设计:基于新兴存储器件的神经形态计算系统故障分析和容错设计研究。


教育背景

1979-1983, Carnegie-Mellon University, Electrical Engineering

1978-1979, California Institute of Technology, Applied Physics

1975-1978, University of California at Berkeley, Physics and Applied Mathematics

1983-1985, Florida Institute of Technology, Master of Business Administration (MBA)


工作经历

2005 to 2022 Georgia Institute of Technology

Professor of Electrical Engineering & Computer Engineering (2005-2020)

Professor emeritus, 2021-present

 

1995-2005 Georgia Institute of Technology

Associate Professor of Electrical Engineering & Computer Engineering (Tenured, 1999) 

Electrical Test Thrust Leader for the NSF Packaging Research Center 1995-2004.

 

1989-1995 University of South Florida

Associate Professor of Electrical Engineering (Tenured, 1995)

Joint appointment in the Center for Microelectronics Research and the Department of Electrical Engineering.

 

1986-1989 Harris Corporation, Government Systems Sector

Advanced Component Test Laboratory Group Leader / Staff/Principal Engineer

Directed a group of 25 engineers and a $10M electronics testing laboratory.

 

1983-1986 Harris Corporation, Government Systems Sector

Associate Principal Engineer

 

Summer 1981 IBM Corp. Research Laboratories, San Jose, Calif.

Academic Associate, Pre-doctoral Fellow

 

Summer 1980 IBM Corp. Research Laboratories, San Jose, Calif.

Academic Associate, Pre-doctoral Fellow


Summer 1977 Intel Corp., Santa Clara, California

Laboratory Assistant


学术兼职(部分)

Prof. Keezer has also provided extensive service to the electronics profession through his participation at IEEE workshops, symposia, and conferences. These notably include:

(1) over 10 years continuous service on the ITC Program Committee,

(2) continuing service on the Intl Mixed Signal Test Workshop (IMSTW),

(3) several years leading the Gigahertz Test Workshop (GTW) as Technical or General Chair, and

(4) services as an author, reviewer, session chair, program committee member on numerous other IEEE-sponsored workshops and conferences.


获奖情况及荣誉

2025, West Lake International Friendship Award from Zhejiang Province Goverment

2024, IEEE Life Fellow

2010, IEEE Fellow

2004, IEEE Computer Society Golden Core Member

Top 10 Journal Papers:

 

[1] A Data-Driven Approach to Online Fault Detection in RRAM-based Neuromorphic Hardware using Adversarial- Inspired Test, M. Cheng, X.-C. Li, and D. Keezer, IEEE Transactions on Very Large Scale Integration Systems, 2026.

 

[2] Bidirectional Time-Frequency Modulation Sampling Technique for High-Efficiency Phase Measurement, C. Wang, S. Liu, Y. Xiao, X. Li, and D. Keezer, IEEE Transactions on Instrumentation and Measurement. 2026.

 

[3] A Low-Loss and Ultra-Wideband Dual-Signal Air-Filled Transmission Line for Terahertz Applications, C. Wang, X.- C. Li and David Keezer, IEEE Trans. Microw. Theory Techn., 2025.

 

[4] Low-Cost 20 Gbps Digital Test Signal Synthesis Using SiGe and InP Logic, D.C. Keezer, C.E. Gray, D. Minier, P. Ducharme, Journal of Electronics Test Theory and Applications (JETTA), January 2010.

 

[5] A 5 Gbps Test System for Wafer-Level Packaged Devices, A. M. Majid, D. C. Keezer, IEEE Trans. on Electrical Packaging Manufacturing (TEPM), Vol.32, No.3, pp. 144-151, July 2009.

 

[6] Source-Synchronous Testing of Multilane PCI Express and Hyper-Transport Buses, D.C. Keezer, D. Minier, P. Ducharme, IEEE Design and Test of Computers, vol. 23, no. 1, pp. 46-57, January 2006.

 

[7] Low-Cost Strategies for Testing Multi-GigaHertz SOPs and Components D.C. Keezer, J.S. Davis, S. Bezos, D. Minier, M.C. Caron, K. Bergman, IEEE Transactions on Advanced Packaging, 2005.

 

[8] Multiplexing ATE Channels for Production Testing at 2.5 Gbps D.C. Keezer, D. Minier, M.C. Caron,

IEEE Design and Test of Computers, Vol.21 No.4, pp. 288-301, July/August 2004.

 

[9] The SOP for Miniaturized, Mixed-Signal Computing, Communication, and Consumer Systems of the Next Decade R.R. Tummala, M. Swaminathan, M. Tentzeris, J. Laskar, G.K. Chang, S. Sitaraman, D. Keezer, D. Guidotti, Z. Huang, K. Lim, L. Wan, S. Bhattacharya, V. Sundaram, F. Liu, P.M. Raj, IEEE Trans. On Adv. Packaging, Vol. 27, No. 2, pp. 250-267, May 2004.

 

[10] Electrical Test Strategies for a Wafer-Level Packaging Technology D.C. Keezer, C.S. Patel, M.S. Bakir, Q. Zhou, J.D. Meindl, IEEE Trans. on Electronics Packaging Manufacturing, Vol. 26, No. 4, pp. 267-272, October 2003.


更新时间:2026-03-26
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